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5-3 cd4000b series this section is intended as a guide for circuit and equipment designers in the operation and application of mos inte- grated circuits. it covers general operating and handling con- siderations with respect to the following critical factors: ? operating supply voltage range ? power dissipation and derating ? system noise considerations ? power source rules ? gate-oxide protection networks ? input signals and ratings ? chip assembly and storage ? device mounting ? testing more speci?c information is then given on signi?cant fea- tures, special design and application requirements, and standard ratings and electrical characteristics for cmos b- series logic circuits, and on cmos special function circuits (special interface and display driver circuits). general operating and handling considerations the following paragraphs discuss some key operating and handling considerations that must be taken into account to achieve maximum advantage of the cmos technology. additional information on the operation and handling of cmos integrated circuits is given in application note an6525, guide to better handling and operation of cmos integrated circuits. see section 8, how to use answer- fax, in this selection guide. operating supply voltage range because logic systems occasionally experience transient con- ditions on the power supply line which, when added to the nominal power-bus voltage, could exceed the safe limits of cir- cuits connected to the power bus, the recommended operat- ing supply voltage range is 3v to 18v for b-series devices. the recommended maximum power supply limit is substan- tially below the minimum primary breakdown limit for the devices to allow for limited power supply transient and regula- tion limits. for circuits that operated in a linear mode over a portion of the voltage range, such as rc or crystal oscillators, a minimum supply voltage of 4v is recommended. power dissipation and derating the power dissipation of a cmos integrated circuit is the sum of a dc (quiescent) component and an ac (dynamic) components. the dc component is the sum of the net inte- grated circuit reverse diode junction current and the surface leakage current times the supply voltage. in standard b- series logic devices, the dc dissipation typically ranges, depending upon device complexity, from 100nw to 400nw for a supply voltage of 10v. worst-case dc dissipation is the product of the maximum quiescent current (given in the data sheet on each device) and the dc supply voltage v dd . dynamic power dissipation has three components: 1. the dissipation that results from current that charges and discharges the external load capacitance of the output buffers. the dissipation of each output buffer is equal to cv 2 f, where c is the load capacitance, v is the supply voltage, and f is the switching frequency of that output. 2. the dissipation that results from current that charges and discharges the internal node capacitances. 3. the dissipation caused by the current spikes through the pmos and nmos transistors in series at the instant of switching. this component amounts to approximately 10% of the total dissipation, shown graphically in the datasheets of most cmos circuits. all cmos devices are rated at 200mw per package at the maximum operating ambient temperature rating (t a ) of 125 o c for all packages. power ratings for temperatures below the maximum operating temperature are shown in the standard cmos thermal derating chart in figure 1. this chart assumes that the device is mounted and soldered (or placed in a socket) on a pc board; there is natural convec- tion cooling, with the pc board mounted horizontally; and the pressure is standard (14.7psia). in addition to the overall package dissipation, device dissipation per output transistor is limited to 100mw maximum over the full package operat- ing temperature range. figure 1. standard cmos thermal derating chart system noise considerations in general, cmos devices are much less sensitive to noise on power and ground lines than bipolar logic families (such as ttl or dtl). however, this sensitivity varies as a function of the power supply voltage, and more importantly as a func- tion of synchronism between noise spikes and input transi- tions. good power distribution in digital systems requires that the power bus have a low dynamic impedance; for this purpose, discrete decoupling capacitors should be distrib- uted across the power bus. a more detailed discussion of cmos noise immunity is provided by application note an6587, noise immunity of b-series cmos integrated cir- cuits. see section 8, how to use answerfax, in this selection guide. 20 40 60 80 100 120 t a , ambient temperature ( o c) 600 500 400 300 200 100 package dissipation (mw) 85 125 slope = 12mw/ o c technical overview
5-4 technical overview power source rules figure 2 shows the basic cmos inverter and its gate-oxide protection network plus inherent diodes. the safe operating procedures listed below can be understood by reference to this inverter. notes: 1. these diodes are inherently part of the manufacturing process. 2. diode breakdown d1 ? 25v d2 ? 50v r2 << r1 figure 2. basic cmos inverter with b-series type protection network 1. when separate power supplies are used for the cmos device and for the device inputs, the device power supply should always be turned on before the independent input signal sources, and the input signals should be turned off before the power supply is turned off (v ss v i v dd as a maximum limit). this rule will prevent over dissipation and possible damage to the d2 input protection diode when the device power supply is grounded. when the de- vice power supply is an open circuit, violation of this rule can result in undesired circuit operation although device damage should not result: ac inputs can be recti?ed by diode d2 to act as a power supply. 2. the power supply operating voltage should be kept safely below the absolute maximum supply rating, as indicated previously. 3. the power supply polarity for cmos circuits should not be reversed. the positive (v dd ) terminal should never be more than 0.5v negative with respect to the negative (v ss ) terminal (v dd - v ss > -0.5v). reversal of polarities will forward-bias and short the structural and protection diode between v dd and v ss . 4. v dd should be equal to or greater than v cc for cmos buffers which have two power supplies (except for the cd40109b, and in particular, for cd4009 and cd4010 cmos-to-ttl down conversion devices). 5. power source current capability should be limited to as low a value as reasonable to assure good logic operation. 6. large values of resistors in series with v dd or v ss should be avoided; transient turn-on of input protection diodes can result from drops across such resistors during switching. gate-oxide protection network a problem occasionally encountered in handling and testing low power semiconductor devices, including mos and small geometry bipolar devices, has been damage to gate oxide v dd in out d2 r1 d1 d1 d2 d2 r2 d1 v ss d1 d1 cos/mos (note 1) (note 1) and/or p-n junctions. figure 3 shows the gate-oxide protec- tion circuits used to protect cmos devices from static elec- tricity damage. application note an6525, guide to better handling and operation of cmos integrated circuits. see section 8, how to use answerfax, in this selection guide. figure 3a. for b-series cmos product figure 3b. for cd4049ub and cd4050b and cd40109b cmos types figure 3c. for cmos transmission gates notes: 1. these diodes are inherently part of the manufacturing process. 2. v cc for cd4049ub and cd4050b 3. diode breakdown d1 ? 25v d2 ? 50v figure 3. gate-oxide protection networks used in harris cmos integrated circuits v dd in out v ss (note 1) (note 1) in out v dd (note 2) v ss (note 1) (note 1) cd4049ub cd40109b cd4050b v dd v ss p-well in/out out/in d1 (note 1) d2 (note 1) (note 1) d1 (note 1) d2 gate 1 gate 2 n-sub
5-5 technical overview input signals and ratings input signals should be maintained with in the power supply voltage range, v ss v i v dd . if the input signal exceeds the recommended input signal swing range, the input current should be limited to 100 m a to minimize cross talk between input signals on adjacent terminals, and also to minimize any reduction in noise immunity. the absolute maximum input current rating of 10ma, shown in the published data, protects the device against the possible occurrence of an induced v dd - v ss latch condition, or dam- age to the input protection diodes. latch-up conditions are explained in application note an6525, guide to better han- dling and operation of cmos integrated circuits. see sec- tion 8, how to use answerfax, in this selection guide. all cmos inputs should be terminated. an exception can be made in the case of unbuffered nor and nand gates where terminating one of the series inputs to the proper polarity will not permit current ?ow caused by a ?oating input. thus tying low one of the inputs of an unbuffered nand gate, or tying high one of the inputs of an unbuffered nor gate will satisfy this requirement. when cmos inputs are wired to edge card connectors with cmos drive coming from another pc board, a shunt resistor in the range of 100kw should be connected to v dd or v ss , as applicable, in case the inputs become unterminated with the power supply on. when cmos circuits are driven by ttl logic, a pull-up resistor should be connected from the cmos input to 5v (further information is given in application note an6602, interfacing cos/mos with other logic families, see sec- tion 8, how to use answerfax, in this selection guide. output rules 1. the power dissipation in a cmos package should not ex- ceed the rated value for the ambient temperature speci- ?ed. the actual dissipation should be calculated when shorting outputs directly to v dd or v ss , driving low im- pedance loads, or directly driving the base of p-n-p or n-p-n bipolar transistor. 2. output short circuits often result from testing errors or im- proper board assembly. shorts on buffer outputs or across power supplies greater than 5v can damage cmos devices. 3. cmos, like active pull-up ttl, can be connected in the wire-or configuration because an on pmos and an on nmos transistor could be directly shorted across the power supply rails. (exception: cd40107b) 4. paralleling inputs and outputs of gates is recommended only when the gates are within the same ic package. 5. output loads should return to a voltage within the supply voltage range v dd to v ss . 6. large capacitive loads (greater than 5000pf) on cmos buffers or high current drivers act like short circuits and may over dissipate output transistors. 7. output transistors may be over dissipated by operating buffers as linear amplifiers or using these types as one shot or astable multivibrators. noise immunity and noise margin the complementary structure of the inverter, common to all cmos logic devices, results in a near-ideal input-output transfer characteristic, with switching point midway (45% to 55%) between the 0 and 1 output logic levels. the result is high dc noise immunity. figure 4 shows a typical transfer curve that may be used to de?ne the dc noise immunity of cmos integrated circuits. the noise immunity voltage (v il or v ih ) is the noise voltage at any one input that does not propagate through the sys- tem. minimum noise immunity for buffered b-series cmos devices is 30%, 30%, and 27%, respectively for supply volt- ages v dd of 5v, 10v, 15v and 20% of v dd for all unbuffered gates. the v il and v ih speci?cations de?ne the maximum permissible additive noise voltage at an input terminal when input signals are within 50mv of the supply rails. figure 4. typical transfer curve for a inverting gate at v dd = 10v noise margin is the difference between the noise-immunity voltage (v il or v ih ) and the output voltage v o . noise margin voltage is the maximum voltage that can be impressed upon an input voltage v in (where v in is the v ol or v oh voltage of the preceding stage) at any (or all) logic i/o terminals with- out upsetting the logic or causing any output to exceed the output voltage (v o ) conditions speci?ed for v il and v ih rat- ings. figure 5 illustrates the noise margin concept in a sim- ple system. minimum noise margins for buffered b-series cmos devices are 1v, 2v, and 2.5v, respectively, for supply voltages 5v, 10v, and 15v. figure 5. noise margin example using inverters v il max v ih min v in 10 9 8 7 6 5 4 3 2 1 v il (typ) v o(high) v out v o(low) v nml = v il (max) - v o(low) v nml = v o(high) - v ih (min) v ih typ 012345678910 v ih = 3.5v v ol = 0.5v v dd = 5v v ol = 0.5v v nml = 1v v il = 1.5v v oh = 4.5v v nml = 1v v ih = 3.5v
5-6 technical overview of the two noise limitation speci?cations (noise immunity and noise margin), noise immunity is more practical for cmos devices because cmos outputs are normally within 50mv of supply rails. noise immunity increases as the input pulse width becomes less than the propagation delay of the circuit. this condition is often described as ac noise immunity. further information on noise immunity is given in application note an6587, noise immunity of b-series cmos integrated circuits. see section 8, how to use answerfax, in this selection guide. clock rise and fall time requirements most cmos clocked devices have maximum rise and fall time ratings (normally 5ms to 15ms). with longer rise or fall times, a device may not function properly because of data ripple through, false triggering problems, etc. some b-series cmos counters have schmitt-trigger shaping circuits built into the clock circuit, removing the restriction for input rise or fall times. long rise and fall times on cmos buffer-type inputs cause increased power dissipation which may exceed device capability for operating power supply voltages greater than 5v. parallel clocking process variations leading to differences in input threshold voltage among random device samples can cause loss of data between certain synchronously clock sequential cir- cuits, as shown in figure 6. this problem can be avoided if the maximum clock rise time (t r c l ) for cascading any two cmos sequential devices is limited in accordance with the following equation: b-series types where t p = t phl or t plh (whichever is smaller) for the unit a in figure 6 as speci?ed on the device data sheet at the speci- ?ed value of v dd and loading conditions. schmitt-trigger cir- cuits such as the cd4093b are an ideal solution to applications requiring wave-shipping. figure 6. error effect that results from a slow clock in cascaded circuits maximum t r c l 0.8 v dd v () 1.15 v ------------------------------- t p ns () = c l c l q1 q2 v dd switching point = 0.3v dd switching point = 0.7v dd proper error dq1 b q2 d a 0.3v dd 0.7v dd note: cascading with slow clock can cause error three-state logic three-state logic can be easily implemented by use of a transmission gate in the output circuit; this technique pro- vides a solution to the wire-or problem in many cases. chip assembly and storage harris cmos integrated circuits are provided in a chip from (h suf?x) to allow customer design of special and complex circuits to suit individual needs. cmos chips are electrically identical to and offer the features of their counterparts sealed in ceramic and plastic packages. the following para- graphs describe mounting considerations, packaging, ship- ping and storage criteria, handling criteria, visual inspection criteria, testing criteria, and bonding pad layout and dimen- sions for each chip. mounting considerations all cmos chips are non-gold backed and require the use of epoxy mounting, conductive silver paste or equivalent is rec- ommended. in any case the manufacturers recommenda- tions for storage and use should be followed. in cmos circuits mos-transistor p-channel substrates (n- type bulk material) are connected to v dd , therefore, when chips are mounted and a conductive paste is used, care must be taken to keep the active substrate isolated from ground or other circuit elements. packing, shipping, and storage criteria solid-state chips, being small in size and unencapsulated, are physically fragile and require special handling consider- ation as follows: ? chips must be stored under proper conditions to insure that they are not subjected to a moist and/or contaminated atmo- sphere that could alter their electrical, physical, or mechani- cal characteristics. after the shipping container is opened, the chip must be stored under the following conditions: - storage temperature, 40 o c max - relative humidity, 50% max - clean, dust-free environment ? the user must exercise proper care when handling chips to prevent even the slightest physical damage to the chip. ? during mounting and lead bonding of chips the user must use proper assembly techniques to obtain proper electri- cal, thermal, and mechanical performance. ? after the chip has been mounted and bonded, any neces- sary procedure must be followed by the user to insure that these non-hermetic chips are not subjected to a moist and contaminated atmosphere which might cause the develop- ment of electrical conductive paths across the relatively small insulating surfaces. in addition, proper consideration must be given to the protection of these devices from other harmful environments which could conceivably affect their performance and/or reliability. handling criteria the user should ?nd the following suggested precautions helpful in handling cmos chips.
5-7 technical overview because of the extremely small size and fragile nature of chips, the equipment designer should exercise care in han- dling these devices. for additional handling considerations for cmos devices, refer to application note an6525, guide to better handling and operation of cmos integrated circuits. see section 8, how to use answerfax, in this selection guide. ? grounding - bonders, pellet pick-up tools, table tops, trim and form tools, sealing equipment, and other equipment used in chip handling should be properly grounded. - the operator should be properly grounded. ? in-process handling - assemblies or subassemblies of chips should be trans- ported and stored in conductive carriers. - all external leads of the assemblies or subassemblies should be shorted together. ? bonding sequence - connect v dd ?rst to external connections, for example, terminal 14 of the cd4001bh. - remaining functions may be connected to their external connections in any sequence. ? testing - transport all assemblies of chips in conductive carriers. - in testing chip assemblies or subassemblies, the opera- tor should be properly grounded. visual inspection criteria all standard commercial cmos chips undergo a visual inspec- tion which is patterned after mil-std-883, method 2010, con- dition b with modi?cations re?ecting cmos requirements. testing criteria cmos chips are dc electrically tested 100% in accordance with the same standards prescribed for harris devices in standard packages. device testing harris cmos circuits are 100% tested by circuit probe in the wafer stage and are 100% tested again after they have been packaged. dc tests of harris devices are performed at 5v, 10v, 15v, and 20v; functionality is checked at 2.8v, 17v, and 20v. sample testing is used to assure adherence to quality requirements and ac speci?cations. static test, high speed functional and dc parametric tests, are performed at wafer and package stages by means of a teradyne 325 test set or equivalent. users should follow the sequences below when testing cmos devices: 1. insert the device into the test socket. 2. apply v dd . 3. apply the input signal. 4. perform the test. 5. on completion of test, remove the input signal. 6. turn off the power supply (v dd ). 7. remove the device from the test socket and insert it into a conductive carrier. cmos devices under test must not be exposed to electrostatic discharge or forward biasing of the intrinsic protective diodes shown in figure 3. detailed information on the techniques employed in the test- ing of harris cmos integrated circuits are described in application note an6532, fundamentals of testing cmos integrated circuits. see section 8, how to use answer- fax, in this selection guide. device mounting integrated circuits are normally supplied with lead-tin plated leads to facilitate soldering into circuit boards. in those rela- tively few applications requiring welding of the device leads, rather than soldering, the devices may be obtained with nickel-plated kovar leads (see mil-i-38535). it should be recognized that this type of plating will not provide complete protection against lead corrosion in the presence of high humidity and mechanical stress. in any method of mounting integrated circuits which involves bending or forming of the device leads, it is extremely impor- tant that the lead be supported and clamped between the bend and the package seal, and that bending be done with care to avoid damage to lead plating. in no case should the radius of the bend be less than the diameter of the lead. it is also extremely important that the ends of bent leads be straight to assure proper insertion through the holes in the printed-circuit board. high voltage b-series cmos integrated circuits harris cd4000b series types have a maximum dc supply voltage rating of -0.5v to 20v, and a recommended operat- ing supply voltage range of 3v to 18v. the major features of this series are as follows: ? high voltage (20v) ratings ? 100% tested for quiescent current at 20v ? 5v, 10v, and 15v parametric ratings ? standardized, symmetrical output characteristics ? maximum input current of 1 m a at 18v over full package temperature range; 100na at 18v and 25 o c ? noise margin (full package temperature range) = 1v at v dd = 5v 2v at v dd = 10v 2.5 v at v dd = 15v ? meets all requirements of jedec tentative standard no. 13b, standard speci?cations for description of b-series cmos devices. jedec minimum standard under the sponsorship of the joint electron devices engi- neering council (jedec) of the electronic industries associ- ation (eia), minimum industrial standards have been established for the maximum ratings, dc and ac electrical
5-8 technical overview characteristics of b-series cmos integrated circuits. the jedec standard (jedec tentative standard no. 13b) de?nes b-series cmos integrated circuits as a uniform fam- ily of both buffered and unbuffered types that have an abso- lute dc supply voltage rating of at least 18v. buffered cmos devices these are types in which the output on impedance is inde- pendent of any and all valid input logic conditions, both pre- ceding and present. all such cmos products are designated by suf?x b following the basic type number. unbuffered cmos devices these are types that meet all b-series speci?cations except that the logical outputs are not buffered and the noise-immu- nity voltages, v il and v ih , are speci?ed as 20% and 80%, respectively, of v dd for operation from 5v, 10v, and 17v and 83%, respectively, of v dd for operation from 15v. all such cmos product are designated by the suf?x ub. the jedec minimum standard also includes in the b-series, cmos types that have analog inputs or outputs and in addi- tion, have maximum ratings and logical input and output parameters that conform to b-series speci?cations wherever applicable. these cmos devices are also designated by the suf?x b. all b-series cmos devices can directly replace their a-series counterparts in most applications. the ub types are high volt- age versions of corresponding a-series (unbuffered) types. commercial a-series types have been obsoleted and replaced by b-series counterparts with only a few exceptions such as the continuing cd4059a types. the absolute maximum rating - jedec table lists the minimum standards established for the maximum ratings and recommended operating conditions for b-series cmos integrated circuits. the dc electrical speci?cation - jedec table shows the jedec standards for the dc electrical speci?cations of cmos b-series integrated circuits. standardized ratings and static characteristics harris b-series cmos integrated circuits meet or exceed the most stringent requirements of the jedec b-series speci?- cations. the absolute maximum ratings table shows the standardized maximum ratings and recommended operating supply voltage range for harris b-series cmos integrated circuits. the standardized dc electrical speci?cations for these devices are shown in the dc electrical speci?cation table. as with the jedec speci?cations, the harris standard- ized characteristics classify the b-series devices into three leakage (quiescent device current) categories. table 1 lists the harris types in each category and indicates types that, although they are still b-series types, differ in one or more static characteristics. the absolute maximum ratings table and the dc electri- cal speci?cation table show that in a number on important respects, harris has established new performance stan- dards for b-series cmos logic circuits. ? tight limits for all packages harris devices used the same set of limits for all package styles. the jedec standard establishes two sets of limits for most dc parameters; a tight set for products having a full operating temperature range of -55 o c to +125 o c (all harris devices), and a relaxed set for products having a limited temperature range of -40 o c to +85 o c. because harris supplies only one premium grade of b-series prod- uct in all package styles (i.e., fall-out chips are not used), all b-series cmos devices are speci?ed to the tight set of limits only. ? improved voltage rating all harris b-series devices are tested to voltages that insure safe operation at the absolute maximum dc supply voltage rating of 20v. this higher rating permits greater derating for reliable 15v operation, permits greater 15v supply tolerance and peak transients, and permits system use to 18v with con?dence. ? wider operating range all harris b-series devices have a recommended maxi- mum operating voltage of 18v. the higher limit permits 18v system supply operation, and also permits wider power source tolerance and transients for supplies nor- mally set up to 18v ? lower leakage current the jedec standard establishes three sets of limits for quiescent device current (i dd ) intended to match chip complexity to device leakage current as realistically as possible. for all three levels of chip complexity, all harris b-series devices (regardless of package) conform to the tighter set of limits established in the standard. in addition, a maxi- mum rating is speci?ed at 20v, as well as at 5v, 10v, and 15v. as a result: - in current limited applications, cmos users can depend on one tight leakage limit independent of package style selected. - customer use of cmos product up through 18v is pro- tected by a published tight leakage current speci?cation at 20v (as well as by an input leakage speci?cation at 18v). ? symmetrical output most harris b-series devices have balanced complemen- tary output drive (i.e., the output high current i oh rating is the same as the output low current i ol rating speci?ed to the tighter set of limits established in the jedec standard. the balanced output provides uniform rise and fall time performance, improved system noise energy (dynamic) immunity, optimum device speed for both output switching low-to-high (t plh ) and output switching high-to-low (t phl ), and in general the identical high and low dc and ac char- acteristics normally associated with a good complemen- tary output drive circuit. mos system design, simulation, and performance are signi?cantly enhanced by equal high and low dc and ac performance ratings and one tight speci?cation limit for all package styles.
5-9 ? improved input current (leakage) ratings all harris b-series devices (regardless of package) have a maximum input leakage current (i in ) rating of 100na spec- i?ed at voltages up to 18v, and a maximum limit of 1 m a at the upper limit of the package temperature range. actually, the 100na rating is a practical speci?cation limited by the inability of commercial test equipment to measure lower currents. laboratory tests show that input leakage cur- rents of harris b-series cmos devices are signi?cantly lower than this limit, typically ranging from 10pa to 100pa. ? buffered and unbuffered gates the new industry standard establishes a suf?x ub for cmos products that meet all b-series speci?cations except that the logical outputs of the devices are not buff- ered and the v il and v ih speci?cations are relaxed. the suf?x b de?nes only buffered output devices in which the output on impedance is independent of any and all valid input logic conditions, both preceding and present. harris supplies both buffered b and unbuffered ub ver- sions of a few popular nor and nand gates to make available to designers the advantages of both. the follow- ing table brie?y compares the features of the two versions, a more detailed coverage of the special features of b- and ub- series cmos gates is provided by application note an6558, understanding buffered and unbuffered cmos characteristics. see section 8, how to use answerfax, in this selection guide. ? reliabilit y harris b-series cmos integrated circuits incorporate the latest improvements in processing technology and plastic and ceramic packaging techniques. product quality is real time controlled using accelerated temperature group qual- ity screening in which measured dc parameters are criti- cized against tight b-series limits. figure 7 through figure 10 show the standardized n- and p-channel drain characteristics for b-series cmos devices, and figure 11 through figure 14 show the nor- malized variation of output source and sink currents with respect to temperature and voltage in these devices. comparison of b and ub characteristic buffered version b unbuffered version ub propagation delay (speed) moderate fast noise immunity/margin excellent good output impedance and output transition time constant variable ac gain high medium output oscillation for slow inputs yes no input capacitance low high figure 7. typical output low (sink) current characteristics figure 8. minimum output low (sink) current characteristics figure 9. typical output high (source) current characteristics 30 25 20 15 10 5 0 51015 v ds , drain-to-source voltage (v) i ol , output low (sink) current (ma) 35 20 ambient temperature, t a = 25 o c gate-to-source voltage, v gs = 15v 5v 10v 15 12.5 10 7.5 5 2.5 0 51015 v ds , drain-to-source voltage (v) i ol , output low (sink) current (ma) 20 gate-to-source voltage, v gs = 15v 10v 5v ambient temperature, t a = 25 o c -30 -25 -20 -15 -10 -5 0 i oh , output high (source) current (ma) gate-to-source voltage, v gs = -5v v ds , drain-to-source voltage (v) -5 -10 -15 -20 -10v -15v ambient temperature, t a = 25 o c technical overview
5-10 figure 10. minimum output high (source) current characteristics figure 11. variation of normalized output low (sink) current i ol and output high (source) current i oh with temperature figure 12. variation of normalized output low (sink) current i ol and output high (source) current i oh with supply voltage figure 13. variation of low-to-high (t tlh ) and high-to- low (t thl ) transition time, and low-to-high (t phl ) propagation delay time with temperature figure 14. variation of low-to-high (t tlh ) and high-to- low (t thl ) transition time with supply voltage figure 15. variation of transition time (t thl , t tlh ) with load capacitance -15 -10 -5 0 i oh , output high (source) current (ma) ambient temperature, t a = 25 o c -10v -15v v ds , drain-to-source voltage (v) -5 -10 -15 -20 gate-to-source voltage, v gs = -5v 2 1 -100 -50 0 50 100 150 t a , ambient temperature ( o c) normalized sink, i ol , and source, i oh , current 1.4 1.2 1 0.8 0.6 0.4 0.2 051015 v dd , supply voltage (v) normalized sink, i ol , and source, i oh , current -100 -75 -50 -25 0 25 50 75 100 125 normalized transition time, t thl , t tlh , and propagation delay time, t phl , t plh 1.4 1.2 1 0.8 0.6 t a , ambient temperature ( o c) v dd , supply voltage (v) 4 3.5 3 2.5 2 1.5 1 0.5 0 2 4 6 8 10 12 14 16 normalized low-to-high, t tlh , and high-to-low , t thl , transition time ambient temperature, t a = 25 o c t thl , t tlh , transition time (ns) c l , load capacitance (pf) 020406080 50 100 150 200 ambient temperature, t a = 25 o c v dd , supply voltage = 5v 100 10v 15v technical overview
5-11 technical overview b-series ac electrical speci?cations b-series ac electrical speci?cations for individual types are under the following conditions: v dd = 5v, 10v, and 15v; t a = +25 o c; c l = 50pf; r l = 200k w ; t r and t f = 20ns. figure 13 shows the variation of b-series ac parameter with temper- ature. figure 14 shows the variation of output transition time with supply voltage. figure 17 shows the variation of the stan- dardized output transition time with load capacitance. maximum propagation delay or transition times for values of c l other than the speci?ed 50pf can be determined by use of the multiplication factor (usually 2) between the typical and maximum values given in the ac speci?cations chart included in the technical data for each device applied to the typical curves, and also shown in the device technical data. b-series ac switching speci?cations the ac electrical speci?cation table de?nes the major cmos ac speci?cations, with reference to the waveforms shown in figure 16 through figure 19. test conditions of v dd , low capacitance (c l ), and input conditions are given for individual types in the published data. cmos special products harris supplies some special cmos products that have operating supply voltage ranges and other characteristics that differ from the standardized data speci?ed for b-series cmos integrated circuits. these special application types include: interface circuits for level shifting applications to interface cmos logic levels with different logic types; display drivers non-multiplexed, 4 digit, 7 segment lcd types containing all the circuitry necessary for driving conventional lcd displays without the need for external components, and a video sync generator function. figure 16. transition times and propagation delay times, combination logic note: outputs should be switching from 10% v dd to 90% v dd in accordance with the device truth table. figure 17. clock pulse rise and fall times and pulse width t phl t plh t thl t tlh 90% 50% 10% 50% 10% inverting output input gnd v dd t r t f 90% v dd clock 90% 50% 10% gnd v dd t r c l t f c l 50% 50% t wl t wh 10% t wl + t wh = fc l 1 figure 18a. figure 18b. figure 18. three-state propagation delay wave shapes and test circuit note: 1. (h) or (l) optional figure 19. setup times, hold times, removal time, and propagation delay times for edge triggered sequential logic circuits 50% 10% 90% v ss v dd 10% 90% 50% 50% output disable output low to off output high to off outputs connected outputs disconnected outputs connected 20ns 20ns t phz t plz v dd v ol v oh v ss 90% 10% t pzh t pzl ic with three- state output other inputs output disable v dd for t plz and t pzl v ss for t phz and t pzh output r l = 1k w c l 50pf t r c l t f c l gnd v dd gnd v dd 50% 90% 10% gnd clock input data input output set, reset or preset v dd 50% 50% 50% 50% 90% 10% 50% 90% t rem t plh t su(h) (note 1) t su(l) (note 1) t tlh t thl t h(l) (note 1) t h(h) (note 1) t phl gnd v dd
5-12 family ratings and speci?cations? absolute maximum ratings jedec standard for dc speci?cations of b-series cmos integrated circuits (note 1 and note 2) dc supply voltage, v dd . . . . . . . . . . . . . . . . . . . . . . -0.5v to +18v dc input voltage, v in . . . . . . . . . . . . . . . . . . . . -0.5v to v dd +0.5v dc input current, i in (for any one input) . . . . . . . . . . . . . . . . . . 10ma storage temperature, t s . . . . . . . . . . . . . . . . . . . . -65 o c to +150 o c caution: stresses above those listed in absolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speci?cation is not implied. recommended operating conditions dc supply voltage, v dd . . . . . . . . . . . . . . . . . . . . . . . +3v to +15v operating temperature range, t a . . . . . . . . . . . . . -55 o c to +125 o c dc electrical speci?cation jedec standard for dc speci?cations of b-series cmos integrated circuits parameters symbol test conditions temp. range v dd (v) (note 3) t low +25 o c (note 4) t high unit min max min typ max min max quiescent device current i dd v in = v ss or v dd all valid input combinations mil 5 - 0.25 - - 0.25 - 7.5 m a 10 - 0.5 - - 0.5 - 15 m a gates 15 - 1 - - 1 - 30 m a comm 5 - 1 - - 1 - 7.5 m a 10 - 2 - - 2 - 15 m a 15 - 4 - - 4 - 30 m a buffers, flip-flops i dd v in = v ss or v dd all valid input combinations mil5-1- -1-30 m a 10 - 2 - - 2 - 60 m a 15 - 4 - - 4 - 120 m a comm 5 - 4 - - 4 - 30 m a 10 - 8 - - 8 - 60 m a 15 - 16 - - 16 - 120 m a msi i dd v in = v ss or v dd all valid input combinations mil 5 - 5 - - 5 - 150 m a 10 - 10 - - 10 - 300 m a 15 - 20 - - 20 - 600 m a comm 5 - 20 - - 20 - 150 m a 10 - 40 - - 40 - 300 m a 15 - 80 - - 80 - 600 m a low level output voltage v ol v in = v ss or v dd |i o | <1 m a all 5 - 0.05 - - 0.05 - 0.05 v 10 - 0.05 - - 0.05 - 0.05 v 15 - 0.05 - - 0.05 - 0.05 v high level output voltage v oh v in = v ss or v dd |i o | <1 m a all 5 4.95 - 4.95 - - 4.95 - v 10 9.95 - 9.95 - - 9.95 - v 15 14.95 - 14.95 - - 14.95 - v ? for speci?c technical information on each individual device type, refer to the appropriate data sheet in harris answerfax. see section 8, how to use answerfax, in this selection guide.
5-13 input low voltage v il v o = 0.5v or 4.5v v o = 1v or 9v v o = 1.5v or 13.5v |i o | <1 m a all 5 - 1.5 - - 1.5 - 1.5 v b types 10 - 3 - - 3 - 3 v 15 - 4 - - 4 - 4 v ub types 5 - 1 - - 1 - 1 v 10 - 2 - - 2 - 2 v 15 - 2.5 - - 2.5 - 2.5 v input high voltage v ih v o = 0.5v or 4.5v v o = 1v or 9v v o = 1.5v or 13.5v |i o | <1 m a all 5 3.5 - 3.5 - - 3.5 - v b types 10 7 - 7 - - 7 - v 15 11 - 11 - - 11 - v ub types 5 4 - 4 - - 4 - v 108-8- -8-v 15 12.5 - 12.5 - - 12.5 - v output low (sink) current i ol v o = 0.4v v in = 0v or 5v v o = 0.5v v in = 0v or 10v v o = 1.5v v in = 0v or 15v mil 5 0.64 - 0.51 - - 0.36 - ma 10 1.6 - 1.3 - - 0.9 - ma 15 4.2 - 3.4 - - 2.4 - ma comm 5 0.52 - 0.44 - - 0.36 - ma 10 1.3 - 1.1 - - 0.9 - ma 15 3.6 - 3.0 - - 2.4 - ma output high (source) current i oh v o = 4.6v v in = 0v or 5v v o = 9.5v v in = 0v or 10v v o = 13.5v v in = 0v or 15v mil 5 -0.25 - -0.2 - - -0.14 - ma 10 -0.62 - -0.5 - - -0.35 - ma 15 -1.8 - -1.5 - - -1.1 - ma comm 5 -0.2 - -0.16 - - -0.12 - ma 10 -0.5 - -0.4 - - -0.3 - ma 15 -1.4 - -1.2 - - -1.0 - ma input current i in v in = 0v or 15v mil 15 - 0.1 - - 0.1 - 1 m a v in = 0v or 15v comm 15 - 0.3 - - 0.3 - 1 m a three-state output leakage current i out max v in = 0v or 15v mil 15 - 0.4 - - 0.4 - 12 m a v in = 0v or 15v comm 15 - 1.6 - - 1.6 - 12 m a input capacitance per unit load c in any input all -----7.5--pf notes: 1. voltages referenced to v ss . 2. reprinted from jedec standard no. 13-b, jedec standard specification for description of b-series cmos devices. 3. t low = -55 o c for military temperature range device, -40 o c for commercial temperature device (all harris devices). 4. t high = +125 o c for military temperature range device, +85 o c for commercial temperature range device. dc electrical speci?cation jedec standard for dc speci?cations of b-series cmos integrated circuits (continued) parameters symbol test conditions temp. range v dd (v) (note 3) t low +25 o c (note 4) t high unit min max min typ max min max family ratings and speci?cations? ? for speci?c technical information on each individual device type, refer to the appropriate data sheet in harris answerfax. see section 8, how to use answerfax, in this selection guide.
5-14 standardized absolute maximum ratings for b-series cmos integrated circuits dc supply voltage, v dd voltage reference to v ss terminal. . . . . . . . . . . . . -0.5v to +20v input voltage, all inputs . . . . . . . . . . . . . . . . . . . -0.5v to v dd +0.5v dc input current, for any one input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10ma lead temperature (during soldering) at distance 1/16in. 1/32in. (1.59mm 0.79mm) from case for 10s max . . . . . . . . . . . . . . . . . . . . . . . . . . . +265 o c power dissipation per, p d t a = -55 o c to +100 o c . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500mw t a = +100 o c to +125 o c . . . derate linearly at 12mw/ o c to 200mw device dissipation per output transistor for t a = full package temperature range (all package test) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mw operating temperature range, t a . . . . . . . . . . . . . -55 o c to +125 o c storage temperature, t stg . . . . . . . . . . . . . . . . . . -65 o c to +150 o c caution: stresses above those listed in absolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speci?cation is not implied. recommended operating conditions supply, voltage range for t a = full package temperature range . . . . . . . +3v to +18v standardized dc electrical speci?cation for b-series cmos integrated circuits parameters symbol test conditions limits +25 o c unit v o (v) v in (v) v dd (v) -55 o c -40 o c +85 o c +125 o c min typ max quiescent device current i dd max - 0, 5 5 0.25 0.25 7.5 7.5 - 0.01 0.25 m a - 0, 10 10 0.5 0.5 15 15 - 0.01 0.5 m a gates, inverters (note 1) - 0, 15 15 1 1 30 30 - 0.01 1 m a - 0, 20 20 5 5 150 150 - 0.02 5 m a buffers, flip- flops, latches, multi-level gates (msi-1 types) (note 1) - 0, 5 5 1 1 30 30 - 0.02 1 m a - 0, 10 10 2 2 60 60 - 0.02 2 m a - 0, 15 15 4 4 120 120 - 0.02 4 m a - 0, 20 20 20 20 600 600 - 0.04 20 m a complex logic (msi-2 types) (note 1) - 0, 5 5 5 5 150 150 - 0.04 5 m a - 0, 10 10 10 10 300 300 - 0.04 10 m a - 0, 15 15 20 20 600 600 - 0.04 20 m a - 0, 20 20 100 100 3000 3000 - 0.08 100 m a output low (sink) current min i ol min 0.4 0, 5 5 0.64 0.61 0.42 0.36 0.51 1 - ma 0.5 0, 10 10 1.6 1.5 1.1 0.9 1.3 2.6 - ma 1.5 0, 15 15 4.2 4 2.8 2.4 3.4 6.8 - ma output high (source) current, min i oh min 4.6 0, 5 5 -6.4 -0.61 -0.42 -0.36 -0.51 -1 - ma 2.5 0, 5 5 -2 -1.8 -1.3 -1.15 -1.6 -3.2 - ma 9.5 0, 10 10 -1.6 -1.5 -1.1 -0.9 -1.3 -2.6 - ma 13.5 0, 15 15 -4.2 -4 -2.8 -2.4 -3.4 -6.8 - ma family ratings and speci?cations? ? for speci?c technical information on each individual device type, refer to the appropriate data sheet in harris answerfax. see section 8, how to use answerfax, in this selection guide.
5-15 family ratings and speci?cations? output voltage low- level v ol max - 0, 5 5 0.05 - 0 0.05 v - 0, 10 10 0.05 - 0 0.05 v - 0, 15 15 0.05 - 0 0.05 v output voltage high-level v oh min - 0, 5 5 4.95 4.95 5 - v - 0, 10 10 9.95 9.95 10 - v - 0, 15 15 14.95 14.95 15 - v input low voltage v il max 0.5, 4.5 - 5 1.5 - - 1.5 v 1, 9 - 10 3 - - 3 v b types 1.5, 13.5 - 15 4 - - 4 v ub types 0.5, 4.5 - 5 1 - - 1 v 1, 9 - 10 2 - - 2 v 1.5, 13.5 - 15 2.5 - - 2.5 v input high voltage v ih max 0.5, 4.5 - 5 3.5 3.5 - - v 1, 9 - 10 7 7 - - v b types 1.5, 13.5 - 15 11 11 - - v ub types 0.5, 4.5 - 5 4 4 - - v 1, 9 - 10 8 8 - - v 1.5, 13.5 - 15 12.5 12.5 - - v input current i in max - 0, 18 18 0.1 0.1 1 1- 10 -5 0.1 m a three-state output leakage current i out max 0, 18 0, 18 18 0.4 0.4 12 12 - 10 -4 0.4 m a note: 1. classi?cations of harris cmos b-series types are shown in table 1. standardized dc electrical speci?cation for b-series cmos integrated circuits (continued) parameters symbol test conditions limits +25 o c unit v o (v) v in (v) v dd (v) -55 o c -40 o c +85 o c +125 o c min typ max ? for speci?c technical information on each individual device type, refer to the appropriate data sheet in harris answerfax. see section 8, how to use answerfax, in this selection guide.
5-16 ac electrical speci?cations de?nitions parameters symbol min max notes propagation delay outputs going high to low t phl -x- outputs going low to high t plh -x- output transition time outputs going high to low t thl -x- outputs going low to high t tlh -x- pulse width set, reset, preset, enable, disable, strobe, clock t wl or t wh x-1 clock input frequency f cl - x 1, 2 clock input rise and fall time t rcl , t fcl -x- set-up time t su x-1 hold time t h x-1 removal time - set, reset, preset-enable t rem x-1 three-state disable delay times high level to high impedance t phz -x- high impedance to low level t pzl -x- low level to high impedance t plz -x- high impedance to high level t pzh -x- notes: 1. by placing a de?ning min or max in front of de?nition, the limits can change from min to max, or vice versa. 2. clock input waveform should have a 50% duty cycle and be such as to cause the outputs to be switching from 10% v dd to 90% v dd in accordance with the device truth table. table 1. classification of harris b-series cmos integrated circuits according to circuit complexity gates/inverters buffers/flip-flop/ latches/multi-level gates (msl-1) complex logic (msi-2) cd4001b cd4069ub cd4009ub (note 1) c04093b cd4006b cd4055b (note 1) cd4532b cd4001ub cd4070b cd4010b (note 1) cd4095b cd4008b cd4056b (note 1) cd4536b cd4002b cd4071b cd4013b CD4096B cd4014b cd4060b cd4541b cd4007ub cd4072b cd4019b cd4098b cd4015b cd4063b cd4543b cd4011b cd4073b cd4027b cd4502b (note 1) cd4017b cd4067b (note 1) cd4555b cd4011ub cd4075b cd4030b cd4503b cd4018b cd4076b cd4556b cd4012b cd4077b cd4041ub (note 1) cd4504b cd4020b cd4089b cd4560b family ratings and speci?cations? ? for speci?c technical information on each individual device type, refer to the appropriate data sheet in harris answerfax. see section 8, how to use answerfax, in this selection guide.
5-17 cd4016b (note 1) cd4078b cd4042b cd4519b cd4021b cd4094b cd4566b cd4023b cd4081b cd4043b cd40106b cd4022b cd4097b (note 1) cd4585b cd4025b cd4082b cd4044b cd40107b (note 1) cd4024b cd4099b cd4724b cd4048b cd40117b cd4047b cd40109b (note 1) cd4026b cd4508b cd14538b cd4066b (note 1) cd4572ub cd4049ub (note 1) cd40174b cd4028b cd4510b cd40100b cd4068b cd4050b (note 1) cd40175b cd4029b cd4511b (note 1) cd40102b cd4085b cd40257b cd4031b cd4512b cd40103b cd4086b cd4033b cd4514b cd40105b cd4034b cd4515b cd40110b (note 1) cd4035b cd4516b cd40147b cd4040b cd4517b cd40160b cd4045b (note 1) cd4518b cd40161b cd4046b (note 1) cd4520b cd40163b cd4051b (note 1) cd4521b cd40192b cd4052b (note 1) cd4522b cd40193b cd4053b (note 1) cd4527b cd40194b cd4054b (note 1) cd4529b note: 1. indicates types for which, because of special design requirements, one or more static characteristics differ from the standardized data. refer to data pages on these types for speci?c differences. table 1. classification of harris b-series cmos integrated circuits according to circuit complexity (continued) gates/inverters buffers/flip-flop/ latches/multi-level gates (msl-1) complex logic (msi-2) family ratings and speci?cations
5-18 enhanced product standard ic circuits suffix x burn-in time (note 1) 160 hours temperature (note 1) +125 o c bias voltage cd4000b 15v special differs by type product identification all enhanced product is identified by a suffix x examples: standard cd4001be enhanced cd4001bex note: 1. or equivalent means equivalent time-temperature /voltage result- ing in the same activation energy. product flow 100% burn-in 160 hrs at +125 o c or equivalent 100% parametric and functional tests at +25 o c sample parametric and functional tests at +25 o c aql = 0.025% enhanced product = product state or process = quality assurance step standard product

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